Balance of a hexapod in real time using a FPGA

Luis M. Aguilar, Juan P. Torres, Christian R. Jimenes, Diego R. Cabrera

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Conference

ConferenceCHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015
Period4/02/16 → …

Fingerprint

Field programmable gate arrays (FPGA)
Robots
Servomotors
Data handling
Accelerometers
Data acquisition
Hardware
Processing

Cite this

Aguilar, L. M., Torres, J. P., Jimenes, C. R., & Cabrera, D. R. (2016). Balance of a hexapod in real time using a FPGA. 825-828. Paper presented at CHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015, . https://doi.org/10.1109/Chilecon.2015.7404667
Aguilar, Luis M. ; Torres, Juan P. ; Jimenes, Christian R. ; Cabrera, Diego R. / Balance of a hexapod in real time using a FPGA. Paper presented at CHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015, .4 p.
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title = "Balance of a hexapod in real time using a FPGA",
author = "Aguilar, {Luis M.} and Torres, {Juan P.} and Jimenes, {Christian R.} and Cabrera, {Diego R.}",
year = "2016",
month = "2",
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doi = "10.1109/Chilecon.2015.7404667",
language = "English",
pages = "825--828",
note = "null ; Conference date: 04-02-2016",

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Aguilar, LM, Torres, JP, Jimenes, CR & Cabrera, DR 2016, 'Balance of a hexapod in real time using a FPGA' Paper presented at CHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015, 4/02/16, pp. 825-828. https://doi.org/10.1109/Chilecon.2015.7404667

Balance of a hexapod in real time using a FPGA. / Aguilar, Luis M.; Torres, Juan P.; Jimenes, Christian R.; Cabrera, Diego R.

2016. 825-828 Paper presented at CHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015, .

Research output: Contribution to conferencePaper

TY - CONF

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AU - Torres, Juan P.

AU - Jimenes, Christian R.

AU - Cabrera, Diego R.

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Aguilar LM, Torres JP, Jimenes CR, Cabrera DR. Balance of a hexapod in real time using a FPGA. 2016. Paper presented at CHILECON 2015 - 2015 IEEE Chilean Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Proceedings of IEEE Chilecon 2015, . https://doi.org/10.1109/Chilecon.2015.7404667